1. Technical Field
The present invention relates to electronic components in general and in particular to multiplexer (hereafter MUX).
2. Description of Related Art
The development and design of functional electrical circuits such as programmable logic array (PLA), application specific integrated circuits (ASICs) etc. are based upon electrical components sometimes called basic building blocks. Among the many building blocks that are used regularly is the MUX. A conventional MUX has at least two inputs, one output and a control terminal. Each of the inputs is associated with a separate and distinct path through the MUX. In this type of MUX the paths are activated sequentially. Stated another way, at any instance of time only one path and associated input is activated while the other input remains inactive. As a consequence, the results on the single output are due to activities on only one of the inputs.
Even though this type of MUX works well for its intended purposes it has one drawback which could limit its use in several types of combinatorial logic design. The drawback is that the prior art MUX generated leakage power resulting in unnecessary heating. The leakage power generation is primarily due to current flow in transistors that are not fully turned off. These partially turned on transistors are in the non-activated path of the MUX. The leakage power drawback will get worse as the geometries of circuits shrink and more MUX are used in a particular design.
Due to the complexity of ASICs design tests methodologies are required to make sure the design functions the way it is suppose to work. There are two methodologies used for testing. One methodology is called Level Sensitive Scan Design (LSSD) and the other is called MUX'ed scan design. One of the applications in which the MUX can be used is the MUX'ed scan design. Other applications that the inventors of the present invention deemed novel are set forth herein after.
FIG. 1a shows a high level diagram for a two to one (2 to 1) MUX consisting of three NAND gates labeled 100, 102 and 104. A capacitive load labeled cload and an output labeled out are connected to NAND gate 104. A data line labeled d1 and a control line labeled sel are connected to NAND gate 100. Similar line labeled d2 and selb are connected to NAND gate 102.
FIG. 1b shows a mixed schematic of high level and circuit level components for a 2 to 1 MUX. For simplicity items and/or components that are identical in FIGS. 1a and 1b are identified by common alphanumeric characters. The circuit level components for NAND gate 104 consist of two PMOS devices 106 and 108 connected in parallel. The source electrodes of devices 106 and 108 are coupled to the positive rail of power supply Vdd. The base electrode of device 106 is connected to d1_sel and the base electrode of NMOS device 112. The source electrode of device 112 is connected to the Ground (Gnd) rail of the power supply. The output from NAND gate 102 is labeled int and is connected to the base electrode of device 108 and 110. The parallel configuration of NMOS devices 106 and 108 is connected to the series configuration of NMOS devices 110 and 112 and output terminal labeled out.
Still referring to FIGS. 1a and 1b this type of latch has two independent transmission paths. One path includes NAND gate 100 and NAND gate 104 responding to signals d1 and sel whereas the other path consisting of NAND gates 102 and 104 respond to signals d2 and sel_b. In some designs the path consisting of NAND gates 102 and 104 can be used as a scan path to test operability of the design. In particular, NAND gate 102 receiving d2 scan in signal becomes useless after the completion of the scan test and dissipates power due to leakage current.
In view of the above, there is a need to provide a MUX that does not consume useless power due to leakage current or other phenomenon.